High-Speed Inter-Chip USB Electrical Specification, Version • Universal Serial Bus Specification, Revision AN Introduction to HSIC. Author. HSIC Device Using Synopsys USB Device Controller and HSIC PHY with the UTMI+ specification; Implements data recovery from serial data on the HSIC. Specification Test Points and Measurement Setup Library. .. For further details on HSIC test specifications and compliance testing.
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High-speed inter-chip HSIC interface is becoming more popular due to its notable advantages over USB for hard-wired sepcification applications. The interface is a two-signal, source-synchronous interface that can provide USB high-speed data at Mbps.
Data transfers are per cent host-driver compatible with traditional USB topologies. Full-speed FS and low-speed LS are not supported by the format. The interface differs from USB in the physical layer only. Significant features include no chirp protocol, source-synchronous serial data transmission and no hot removal or attach as the interface is always connected.
Maximum trace length is 10cm. The primary difference between the two is that in HSIC all information is transmitted via a single data line, and a strobe signal communicates when to sample the received data signal. HSIC uses double data rate DDR signalling; data are sampled at both the rising and falling edges of the strobe signal.
The strobe signal oscillates at a frequency of MHz, which provides a total data rate of Mbps. For a start, it is a fully-digital standard and, thus, no analogue frontend is required.
Lack of an analogue frontend speciifcation die sizes can be reduced and, thus, so can the cost. Additional die reduction can also be made due to the decreased amount of digital logic required by the simplified connection protocol. HSIC standard does not inherently reduce power consumption, but removal of the analogue frontend can lead to lower-power designs, especially since analogue circuitry does not necessarily scale one-to-one with digital circuits for reductions in process feature size.
HSIC is especially low-power when placed into the suspended state as there is no current drawn on the strobe speecification data lines. With standard USB, every data packet begins with a sync pattern to allow the receiver clock to synchronise with the phase of incoming data. HSIC uses a separate strobe line to tell the hsiic when to sample incoming data.
Data Interface: HSIC versus USB
HSIC specificatiln signal is sampled at the rising and falling edges of the strobe signal. If the strobe and data signals become skewed for any reason, sampled data may become corrupted. To make sure the skew does not become an issue, HSIC traces must be kept as short as possible and must not be longer than 10cm.
To illustrate the amount of skew possible in the real world, Fig. The same packet transmitted from the same host with a strobe trace that is about 10cm longer than the data trace is shown in Fig. The resulting skew is about half of a nanosecond. This is an extreme example, but specifiction suggest that even a small amount of length mismatch may result in an HSIC specification violation.
The single-ended nature and differences in signal termination cause some difficulties when attempting to probe HSIC lines. Standard USB signals can be easily monitored and deciphered by placing a differential probe connected to an oscilloscope at either the transmitter side or the receiver side. HSIC signals are more sensitive and, thus, transmission line theory should be considered when attempting to probe these.
A good general guideline is to probe at the side opposite to the specificatino of the signal that specifiication to be observed.
InterChip USB – Wikipedia
For instance, to observe the signals originating from a device, place a probe at host-side terminals.
To observe the specifjcation originating from a host, place the probes at device-side terminals. When attempting to probe signals originating from a device while probing at the device side, the signal becomes distorted. This is likely due to the interference caused by the signal reflecting back on itself.
The middle of the trace can also be probed, but results are typically not as clean as if probed properly from one side. The ideal would be to probe simultaneously from both ends. A series protocol analyser may be able to sample the signals accurately in both directions, but the 10cm trace length restriction makes this option impractical.
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