PIN NAMES. LOADING (Note a). HIGH. LOW. PE. Parallel Enable (Active LOW) Input. U.L.. U.L.. P0 – P3. Parallel Data Inputs. U.L.. U.L. Data sheet acquired from Harris Semiconductor. SCHSE. Features. • Asynchronous Master Reset. • J, K, (D) Inputs to First Stage. • Fully Synchronous Serial. EA. ACTIVE. CDIP. J. 1. TBD. A N / A for Pkg Type. to EA. SNJ54SJ. FA. ACTIVE. CFP. W. 1.

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74LS 4-bit Parallel-Access Shift Register

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series integrated circuits included in Altera Quartus II library ‘/others/maxplus2/’

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